• Even though we have this part in stock, it may take several days for internal process to complete. Goods will be delivered within 5 -7 working days. 聽

• Manufacturer: Mitsubishi Electric

• Q04UDVCPU

• control method : Stored program repeat operation

• Input-output control system : Refresh method

(direct access input and output (DX, DY) direct access input and output allowed by the specification of)

• Programming language : Relay symbol language, logic symbolic language, MELSAP3 (SFC), MELSAP-L, function block, structured text (ST)

• Peripheral device connection port : USB, Ethernet

• Memory card interface : Yes (SD memory card)

• Processing speed : 1.9ns, 3.9ns

• Constant scan : 0.5 ~ 2000ms (settable in 0.1ms units)

• Program capacity : 40K step (160K bytes)

• Memory capacity : 160K bytes

• Mounting SD memory card (SD / SDHC) capacity minute (maximum 32G bytes)

• 256K bytes

The capacity of the expansion SRAM cassette unused when capacity + expansion SRAM cassette

(extended SRAM cassette maximum 8M bytes)

• When expanded SRAM cassette unused : 1025.5K bytes

• When using extension SRAM cassette : 8K bytes

• QCPU standard area : 8K bytes

• Multi-CPU between the high-speed communication area : 124 present

• Maximum storage file number :

• Root folder: maximum 512

subdirectory: maximum 65534 present

Root folder: maximum 65535 this

subdirectory: Up to 65534 this

• SD : 323 present

• SDHC : 256

• Intelligent function module parameter setting maximum number : 4096, 2048

• Write the number of program memory : Up to 10 million times

• Write the number of standard ROM : Up to 10 million times

• Input and output device points : 8192 points (X / Y0 ~ 1FFF)

• O points : 4096 points (X / Y0 ~ FFF)

• Device points :

• Default 15360 points (M0 ~ 15359) (changed)

• Default 8192 points (L0 ~ 8191) (changed)

• Default 8192 points (B0 ~ 1FFF) (changed)

• Default 2048 points (T0 ~ 2047) (shared low-speed timer / Fast Timer) (changed)

the low-speed timer / high speed timer is specified in the instruction

set unit of measurement of the low-speed timer / high speed timer in the parameters

(low-speed timer: 1 ~ 1000ms , 1ms increments, the default 100 ms)

(high-speed timer: 0.01 ~ 100ms, 0.01ms unit, default 10.0ms)

• Default 0 points (slow integration timer / Fast integration timer shared) (changed)

the slow integration timer / Fast integration timer is specified in the instruction

set unit of measure of the slow integration timer / Fast integration timer in the parameters

(low-speed integrated timer: 1 ~ 1000ms, 1ms unit, default 100 ms)

(Fast integration timer: 0.01 ~ 100ms, 0.01ms unit, default 10.0ms)

• Normal counter: default 1024 points (C0 ~ 1023) (changed)

• Default 22528 points (D0 ~ 22527) (changed)

• Default 0 points (changed)

• Default 8192 points (W0 ~ 1FFF) (changed)

• Default 0 points (changed)

• Default 2048 points (F0 ~ 2047) (changed)

• Default 2048 points (V0 ~ 2047) (changed)

• 32768 points (R0 ~ 32767)

by the block switching, usable up to a maximum of 131072 points

32768 points (R0 ~ 32767)

by the block switching, usable up to a maximum of 655 360 points

32768 points (R0 ~ 32767)

by the block switching, usable up to a maximum of 1,179,648 points

32768 points (R0 ~ 32767)

by the block switching, usable up to a maximum of 2,228,224 points

32768 points (R0 ~ 32767)

by the block switching, usable up to a maximum of 4,325,376 points

• When expanded SRAM cassette unused :

• Q4MCA-1MBS during use : 131072 points (ZR0 ~ 131071)

block switching unnecessary

• Q4MCA-2MBS during use : 1179648 points (ZR0 ~ 1179647)

block switching unnecessary

• Q4MCA-4MBS during use : 2228224 points (ZR0 ~ 2228223)

block switching unnecessary

• Q4MCA-8MBS during use : 4325376 points (ZR0 ~ 4325375)

block switching unnecessary

• When expanded SRAM cassette unused : Default 2048 points (SB0 ~ 7FF) (changed)

• Q4MCA-1MBS during use : Default 2048 points (SW0 ~ 7FF) (changed)

• Q4MCA-2MBS during use : Default 8192 points (S0 ~ 8191) (changed)

• Q4MCA-4MBS during use : Maximum 20 points (Z0 ~ 19)

• Q4MCA-8MBS during use :

• Up to 10 points (Z0 ~ 18) (used in the double word the index register [Z])

• 4096 points (P0 ~ 4095) (device points is fixed)

setting allowed the range of use of local pointer / Common pointer by the parameter

• Point 256 (I0 ~ 255) (device points is fixed)

settable constant cycle interval of system interrupt pointer I28 ~ 31 by the parameter (0.5 ~ 1000.0ms, 0.5ms unit)

default I28: 100ms, I29: 40ms, I30: 20ms , I31: 10ms

• Point 2048 (SM0 ~ 2047) (device points is fixed)

• Point 2048 (SD0 ~ 2047) (device points is fixed)

• 16 points (FX0 ~ F) (device points is fixed)

• 16 points (FY0 ~ F) (device points is fixed)

• 5 points (FD0 ~ 4) (device points is fixed)

• Link direct device : Devices directly access the link device

CC-Link IE, MELSECNET / H dedicated

specified format: J X , J Y , J W , J B , J SW , J SB

• Intelligent function module device : Device to access the buffer memory of intelligent function unit directly

specified format: U G

• Latch (power outage holding) range : L0 ~ 8191 (default 8192 points)

[B, F, V, T, ST, C, D, and latches the range settable for W]

• RUN / PAUSE contact : X0 ~ RUN / PAUSE contact each one-point configurable than 1FFF

• Clock function : Year, month, day, hour, minute, second, day of the week (leap year automatic discrimination)

accuracy: -2.97 ~ + 3.75s (. TYP + 0.39s) / d at 0

accuracy: -2.97 ~ + 3.75s (TYP +. 0.39s) / d at 25

accuracy:. -12.77 ~ + 2.13s (TYP -5.32s) / d at 55

• Allowable momentary power failure time : By the power supply unit

• DC5V internal current consumption : 0.58A (CPU unit alone) /0.6A (when expanded SRAM cassette loading)

• External dimensions : 98mm x 27.4mm x 115mm

• Transmission Specifications : -

• 100 / 10Mbps

• Full / half duplex

• Baseband

• 100m

• 10BASE-T : Cascade up to four stages

• 100BASE-TX : Cascade up to two-stage

• Number of connections : Socket communication, MELSOFT connection, a total of 16 MC protocol

one for FTP

• Shipping Weight: 1.5 Kg